Integrated circuit memory devices having hierarchical bit line selection circuits therein

ABSTRACT

Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

REFERENCE TO PRIORITY APPLICATION

This application claims priority to Korean Application Serial No.2004-75252, filed Sep. 20, 2004, the disclosure of which is herebyincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methodsof operating same and, more particularly, to integrated circuit memorydevices and methods of operating same.

BACKGROUND OF THE INVENTION

Conventional memory devices include a class of memory devices referredto as static random access memory (SRAM) devices. As illustrated by FIG.1, a conventional SRAM device 100 includes a plurality of column units101 arranged side-by-side in a semiconductor substrate. Each of thecolumn units 101 is illustrated as including a column of SRAM cells 107,a bit line precharging and equalization circuit 109, which is responsiveto an active low bit line precharge signal /PBL, and a bit lineselection circuit 111, which is responsive to a pair of column selectionsignals Y and /Y. The column of SRAM cells 107 is electrically coupledto a corresponding pair of bit lines (BL and /BL) and each SRAM cellwithin the column 107 is responsive to a corresponding word line signal(SWL1–SWLn). The bit line precharging and equalization circuit 109includes PMOS transistors P1–P3 and the bit line selection circuit 111includes transmission gates TG1 and TG2. As will be understood by thoseskilled in the art, setting the bit line precharge signal /PBL lowduring a precharge time interval causes both bit lines BL and /BL to beequalized at a logic 1 voltage level (e.g., Vdd). In addition, settingthe bit line precharge signal /PBL high and the true column selectionsignal Y high (and /Y low) will cause the pair of bit lines BL and /BLto be connected to a pair of data lines DL and /DL. During a readoperation, these data lines DL and /DL provide read data to a senseamplifier 103 and a data output buffer 113 within a read path of thememory device. During a write operation, the data lines DL and /DLreceive write data from a write driver 105, which is electricallycoupled to a data input buffer 115.

As illustrated by the timing diagram of FIG. 2, a leading edge of aclock signal CLK (for a synchronous SRAM device) or an address ADD (foran asynchronous SRAM device) may result in the switching of the wordline, column selection and bit line precharge signals illustrated byFIG. 1. In particular, prior to receipt of a leading edge of the clocksignal CLK (or address ADD), the bit line precharge signal /PBL is heldlow and the pair of bit lines BL and /BL are held high at logic 1voltage levels. Then, upon receipt of the leading edge, the bit lineprecharge signal /PBL is switched high to an inactive level, a selectedword line SWL1 is switched high to activate a row of SRAM cells and thecolumn selection signals Y and /Y are set high and low, respectively, tothereby electrically couple the pair of bit lines BL and /BL to thecorresponding pair of data lines DL and /DL. These switching operationsresult in a transfer of differential read data from a selected memorycell to the corresponding bit lines BL and /BL and then to thecorresponding data lines DL and /DL. This differential read data is thendetected and amplified by the sense amplifier 103 and output to the dataoutput buffer 113.

A possible layout of the SRAM device 100 of FIG. 1 is illustrated byFIG. 3. In particular, FIG. 3 illustrates an SRAM device having acapacity of 16K bits by 16K bits, with each sub-block of 1K bits by 2Kbits worth of memory being arranged as 2048 rows of SRAM cells extendingin a horizontal word line direction by 1024 columns of SRAM cellsextending in a vertical bit line direction. Each sub-block is associatedwith a corresponding bit line control circuit and peripheral circuit.Unfortunately, the bit line capacitance associated with each pair of bitlines (BL and /BL), which span 2048 rows of SRAM cells, may be excessiveand thereby increase active power (i.e., switching power) and accesstime during reading and writing operations.

To address these problems of excessive active power and access time,integrated circuit memory devices may utilize hierarchical bit lineselection circuits that reduce bit line capacitance. In some of thesememory devices, two or more SRAM cells may be used in combination todivide a bit line into two or more sub bit-lines, which are combined toform two or more levels of hierarchy. One such memory device isdisclosed in an article by A. Karandikar et al., entitled “Low PowerSRAM Design Using Hierarchical Divided Bit-Line Approach,” ICCDProceedings, pp. 82–88, October 1998. In particular, the Karandikar etal. article illustrates how the drain capacitance loading on a bit linecan be reduced by reducing the number of access transistors connected tothe bit line by a factor of four or more. However, this advantageousreduction in bit line capacitance typically incurs a layout area penaltybecause additional column decoding and related circuits are required tocontrol the additional access transistors at the multiple levels ofhierarchy. U.S. Pat. No. 5,715,189 to Asakura also discloses a memorydevice having a hierarchical bit line arrangement.

Conventional techniques to achieve reductions in layout area of SRAMmemory devices are disclosed in an article by S. M. Jung et al.,entitled “The Revolutionary and Truly 3-Dimensional 25F² SRAM Technologywith the Smallest S³ (Stacked Single-Crystal Si) Cell, 0.16 um², andSSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra HighDensity SRAM,” Symposium on VLSI Technology Digest, pp. 228–229, June2004, the disclosure of which is hereby incorporated herein byreference. In this article, an SRAM cell having a reduced cell size isdescribed as having two thin-film PMOS load transistors and twothin-film NMOS pass transistors stacked over two planar NMOS pull-downtransistors. In particular, FIG. 3 of this article shows a 6T SRAM cellhaving a pair of NMOS bulk transistors, a pair of PMOS load transistorson an interlayer dielectric layer (ILD1) and a pair of NMOS accesstransistors on another interlayer dielectric layer (ILD2).

SUMMARY OF THE INVENTION

Integrated circuit memory devices according to embodiments of theinvention utilize hierarchical bit line selection circuits to reduceactive power requirements by lowering bit line capacitance. These memorydevices also include arrangements of stacked thin-film transistors(TFTs), which reduce the layout area requirements of bit line prechargeand selection circuits. According to some of these embodiments of theinvention, a memory device includes at least a first column of memorycells electrically coupled to a first pair of bit lines. A bit lineprecharge and selection circuit is also provided. This bit lineprecharge and selection circuit includes a stacked arrangement of afirst PMOS pull-up transistor and a first NMOS pass transistorelectrically coupled to one of the first pair of bit lines. This stackedarrangement of transistors may be disposed above a memory core portionof a semiconductor substrate and thereby reduce the presence ofalternating P-type and N-type conductivity regions within the memorycore portion. This reduction in alternating P-type and N-typeconductivity regions operates to inhibit an occurrence of parasiticlatch-up, which may result in potentially destructive regenerativecurrent conduction within the substrate.

According to preferred aspects of these embodiments, the first PMOSpull-up transistor is a PMOS TFT and the first NMOS pass transistor isan NMOS TFT. The first current carrying terminal of the PMOS TFT iselectrically connected to a first current carrying terminal of the NMOSTFT and a true one of the first pair of bit lines. A gate terminal ofthe PMOS TFT is electrically connected to a gate terminal of the NMOSTFT. A second current carrying terminal of the PMOS TFT is electricallyconnected to a power supply line (Vdd) and a second current carryingterminal of the NMOS TFT is electrically connected to a global bit line.

Other embodiments of the invention include an integrated circuit memorydevice having at least first and second columns of memory cells therein,which are electrically coupled to first and second pairs of bit lines,respectively, and a first bit line precharge and selection circuit. Thisfirst bit line precharge and selection circuit includes a stackedarrangement of a first PMOS TFT and a first NMOS TFT electricallycoupled to a true one of the first pair of bit lines and a stackedarrangement of a second PMOS TFT and a second NMOS TFT electricallycoupled to a complementary one of the first pair of bit lines. A pair ofglobal bit lines is electrically coupled to the first and second NMOSTFTs. The memory device also includes a pair of data lines and aprecharge and equalization circuit electrically coupled to the pair ofglobal bit lines. In addition, a global bit line selection circuit isprovided, which is electrically coupled to the precharge andequalization circuit and the pair of data lines.

Still further embodiments of the invention include a first column of TFTSRAM cells electrically coupled to a first pair of bit lines. These TFTSRAM cells may include two thin-film PMOS load transistors and twothin-film NMOS pass/access transistors stacked over two planar NMOSpull-down transistors, which are disposed within a semiconductorsubstrate. A bit line precharge and selection circuit is provided. Thiscircuit includes a stacked arrangement of a first PMOS TFT and a firstNMOS TFT electrically coupled to one of the first pair of bit lines. Afirst current carrying terminal (e.g., drain) of the PMOS TFT iselectrically connected to a first current carrying terminal of the NMOSTFT and a true one of the first pair of bit lines. A gate terminal ofthe PMOS TFT is electrically connected to a gate terminal of the NMOSTFT. A second current carrying terminal (e.g., source) of the PMOS TFTis electrically connected to a power supply line and a second currentcarrying terminal of the NMOS TFT is electrically connected to a globalbit line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical schematic of a conventional SRAM device.

FIG. 2 is a timing diagram that illustrates operation of the SRAM deviceof FIG. 1.

FIG. 3 is a block diagram of a 16K by 16K conventional SRAM device.

FIG. 4 is an electrical schematic of an integrated circuit memory deviceaccording to embodiments of the present invention.

FIG. 5 is a timing diagram that illustrates operation of the memorydevice of FIG. 4.

FIG. 6 is a cross-sectional view of a stacked thin-film transistorstructure according to embodiments of the present invention.

FIG. 7A is a block diagram of a 16K by 16K memory device according toembodiments of the present invention.

FIG. 7B is a block diagram of another 16K by 16K memory device accordingto embodiments of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully herein withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity of description. It will also be understood that when a layer isreferred to as being “on” another layer or substrate, it can be directlyon the other layer or substrate, or intervening layers may also bepresent. Like reference numerals refer to like elements throughout.Signals may also be synchronized and/or undergo minor boolean operations(e.g., inversion) without being considered different signals. The suffixB (or prefix symbol “/”) to a signal name may also denote acomplementary data or information signal or an active low controlsignal, for example.

Referring now to FIG. 4, an integrated circuit memory device 1000according to an embodiment of the present invention includes a pluralityof equivalent global column units 500–500 m connected to a pair ofdifferential data lines DL and /DL. Data provided to the data lines DLand /DL during read operations is sensed and amplified by a senseamplifier 402 and passed to a data output buffer 404. During writeoperations, write data is received by a data input buffer 408 and thenpassed to a write driver 406, which drives the data lines DL and /DL.Each of the global column units includes a plurality of partial columnunits 410–410 n connected to a pair of global bit lines GBL and /GBL.The first partial column unit 410 includes a column 412 of SRAM memorycells 4121 coupled to a pair of partial bit lines PBL and /PBL. Thiscolumn 412 of SRAM memory cells 4121 is illustrated as including 1 to nrows of SRAM memory cells 4121, which are electrically coupled torespective ones of the word lines SWL1-SWLn. These SRAM memory cells4121 may be thin-film transistor (TFT) SRAM cells, which utilize anarrangement of thin-film transistors stacked on top of planartransistors. In particular, each of these TFT SRAM cells may be a 6Tcell including two TFT P-type pull-up transistors and two TFT N-typeaccess transistors stacked over two planar field effect transistors,which are disposed within a semiconductor substrate. An exemplaryembodiment of a six transistor (6T) TFT SRAM cell is disclosed in theaforementioned S. M. Jung article, which is hereby incorporated hereinby reference. The pair of partial bit lines PBL and /PBL electricallycouples the column 412 of SRAM memory cells 4121 to a partial bit lineprecharging circuit 414 and a partial bit line selection circuit 416.The partial bit line precharging circuit 414 is illustrated as includinga pair of PMOS pull-up transistors P44 and P45 and the partial bit lineselection circuit 416 is illustrated as including a pair of NMOS passtransistors N41 and N42. The gate terminals of these transistors N41,N42, P44 and P45 are connected to a partial column selection line PY1.When the partial column selection line PY1 is switched high-to-lowduring a precharge time interval, the pair of partial bit lines PBL and/PBL are precharged to a logic 1 voltage level (e.g., Vdd). However,when the partial column selection line PY1 is switched low-to-high, theNMOS pass transistors N41 and N42 are turned on to thereby electricallyconnect the partial bit lines PBL and /PBL to the global bit lines GBLand /GBL. The low-to-high switching of the partial column selection linePY1 preferably includes driving the partial column selection line PY1 toa boosted voltage level Vpp. The value of this boosted voltage level Vppmay equal a sum of the power supply voltage Vdd (e.g., 1.2 Volts) andVth (e.g., 0.6 Volts), where Vth equals a threshold voltage of the NMOSpass transistors N41 and N42. Driving the partial column selection linePY1 to a boosted voltage level Vpp enables each of the global bit linesGBL and /GBL to support a full rail logic 1 voltage during readoperations and enables each of the partial bit lines PBL and /PBL tosupport a full rail logic 1 voltage during write operations.

The data path associated with the global column unit 500 also includes aglobal bit line precharging and equalizing circuit 420 and a global bitline selection circuit 430. The global bit line precharging andequalizing circuit 420 includes PMOS pull-up transistors P41 and P42 anda PMOS equalizing transistor P43. The source terminals of the PMOSpull-up transistors P41 and P42 are electrically connected to a powersupply line Vdd and the drain terminals of the PMOS pull-up transistorsP41 and P42 are electrically connected to the global bit lines GBL and/GBL. The source and drain terminals of the PMOS equalizing transistorP43 are also electrically connected to the drain terminals of the PMOSpull-up transistors P41 and P42. The gate terminals of the PMOStransistors P41–P43 are responsive to an active low global columnselection signal /GY. The global bit line selection circuit 430 includesa pair of transmission gates TG41 and TG42, which are electricallycoupled to the pair of data lines DL and /DL. These transmission gatesare responsive to the column selection signals Y and /Y.

As illustrated by FIG. 5, operation of the global column unit 500 ofFIG. 4 may be synchronized with a clock signal CLK (for a synchronousSRAM device) or an address ADD (for an asynchronous SRAM device). Inadvance of a leading edge of the clock signal CLK (or address ADD), thepair of partial bit lines PBL and /PBL and the pair of global bit linesGBL and /GBL may be precharged to logic 1 voltage levels by switchingthe partial column selection line PY1 low and also switching the globalcolumn selection signal /GY low. Thereafter, in response to the leadingedge of the clock signal CLK (or address ADD), the partial columnselection line PY1 is switched high to the boosted voltage level (e.g.,PY1=Vpp) to thereby electrically connect the pair of partial bit linesPBL and /PBL to the pair of global bit lines GBL and /GBL and terminatethe precharging operation. After a time interval of t1, the word line(e.g., SWL1) for an addressed row of SRAM cells is driven high (e.g.,1.5 Volts) so that data within the selected SRAM cell 4121 is passed tothe corresponding pair of partial bit lines PBL and /PBL. The globalcolumn selection signal line /GY and the true column selection signal Yare also switched low-to-high (e.g., /GY=Y=Vdd) to terminate prechargingof the pair of global bit lines GBL and /GBL and enable data on the pairof partial bit lines PBL and /PBL to be passed to the pair of global bitlines GBL and /GBL and to the pair of data lines DL and /DL. This readdata is then sensed and amplified as a rail-to-rail signal by the senseamplifier 402.

After a sufficient amount of time, the selected word line SWL1, the truecolumn selection signal Y and the global column selection signal line/GY are switched high-to-low. This causes the global bit lines GBL and/GBL to be precharged and disconnected from the pair of data lines DLand /DL. Then, after a time interval of t2, the partial column selectionsignal line PY1 is switched high-to-low to again precharge the partialbit lines PBL and /PBL. The above-described read operations may then berepeated for another row of memory cells 4121.

One 16k by 16k embodiment of the memory device 1000 of FIG. 4 isillustrated by FIG. 7A. This memory device 1000′ of FIG. 7A is arrangedinto four 8k by 8k quadrants. Each of these quadrants includes eight 1kbit global column units. As illustrated, the word lines (SWLn) and theglobal bit lines (GBL and /GBL) extend parallel to each other, but in anorthogonal direction relative to the partial bit lines (PBL and /PBL).The shaded regions illustrate a global bit line control circuit andperipheral circuit. The global bit line control circuit includes theglobal bit line precharging and equalizing circuits 420 and the globalbit line selection circuits 430 illustrated by FIG. 4. Another 16k by16k embodiment of the memory device 1000 of FIG. 4 is illustrated byFIG. 7B. This memory device 1000″ of FIG. 7B is arranged into four 8k by8k quadrants. Each of these quadrants includes eight 1k bit globalcolumn units. As illustrated, the word lines (SWLn) and the global bitlines (GBL and /GBL) are orthogonal to each other, and the global bitlines and the partial bit lines (PBL and /PBL) are parallel to eachother. The shaded regions illustrate a global bit line control circuitand peripheral circuit. The global bit line control circuit includes theglobal bit line precharging and equalizing circuits 420 and the globalbit line selection circuits 430 illustrated by FIG. 4.

As illustrated by FIG. 6, the PMOS pull-up transistor P44 and the NMOSpass transistor N41 of FIG. 4 may be configured as thin-film transistors(TFTs), which are stacked vertically on a semiconductor substrate 600(e.g., P-type substrate). Although not shown, the PMOS pull-uptransistor P45 and the NMOS pass transistor N42 may also be configuredas stacked thin-film transistors (TFTs) that are disposed side-by-siderelative to the stacked transistors illustrated by FIG. 6. Accordingly,all the transistors within the partial bit line precharging circuit 414and the partial bit line selection circuit 416 of FIG. 4 may be formedas a closely stacked arrangement of two pairs of single-crystal TFTs.The formation of these TFT transistors above the substrate 600 mayeliminate a need to form alternating P-type and N-type conductivityregions within a portion of the substrate and thereby inhibit anyoccurrence of parasitic latch-up, which may result in regenerativecurrent conduction within the substrate 600.

In FIG. 6, a P-type well region 610 is shown as being disposed withinthe semiconductor substrate 600. A plurality of interlayer dielectriclayers are also provided on the substrate 600. These dielectric layersinclude a first interlayer dielectric layer 620 (ILD1), a secondinterlayer dielectric layer 630 (ILD2), a third interlayer dielectriclayer 640 (ILD3) and a fourth interlayer dielectric layer 680 (ILD4).The PMOS pull-up transistor P44 is defined by a single crystal siliconactive layer 622 having source, drain and channel regions therein. Thissingle crystal silicon active layer 622 is shown as being directly onthe first interlayer insulating layer 620. A gate electrode of the PMOSpull-up transistor P44 includes a gate insulating pattern 624, a gatepattern 626 and sidewall spacers 628. The NMOS pass transistor N41 isdefined by a single crystal silicon active layer 632 having source,drain and channel regions therein. This single crystal silicon activelayer 632 is shown as being directly on the second interlayer insulatinglayer 630 and stacked above the PMOS pull-up transistor P44. A gateelectrode of the NMOS pass transistor N41 includes a gate insulatingpattern 634, a gate pattern 636 and sidewall spacers 638.

A contact to the drain of the PMOS pull-up transistor P44 and a firstcurrent carrying terminal of the NMOS pass transistor N41 is provided bya partial bit line conductive via 650, which is electrically connectedto a partial bit line PBL (not shown in FIG. 6). A contact to the sourceof the PMOS pull-up transistor P44 is provided by a power supply lineconductive via 670, which is electrically connected to a power supplyline Vdd (not shown in FIG. 6). A contact to a second current carryingterminal of the NMOS pass transistor N41 is provided by a global bitline conductive via 660, which is electrically connected to a global bitline GBL (not shown in FIG. 6).

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. An integrated circuit memory device, comprising: a first column ofmemory cells electrically coupled to a first pair of bit lines; and abit line precharge and selection circuit comprising a stackedarrangement of a first PMOS pull-up transistor and a first NMOS passtransistor electrically coupled to one of the first pair of bit lines.2. The memory device of claim 1, wherein at least one of the first PMOSpull-up transistor and the first NMOS pass transistor is a thin-filmtransistor.
 3. The memory device of claim 1, wherein the first PMOSpull-up transistor is a PMOS thin-film transistor and the first NMOSpass transistor is an NMOS thin-film transistor.
 4. The memory device ofclaim 3, wherein a first current carrying terminal of the PMOS thin-filmtransistor is electrically connected to a first current carryingterminal of the NMOS thin-film transistor and a true one of the firstpair of bit lines.
 5. The memory device of claim 4, wherein a gateterminal of the PMOS thin-film transistor is electrically connected to agate terminal of the NMOS thin-film transistor.
 6. The memory device ofclaim 5, wherein a second current carrying terminal of the PMOSthin-film transistor is electrically connected to a power supply lineand a second current carrying terminal of the NMOS thin-film transistoris electrically connected to a global bit line.
 7. An integrated circuitmemory device, comprising: first and second columns of memory cellselectrically coupled to first and second pairs of bit lines,respectively; a first bit line precharge and selection circuitcomprising: a stacked arrangement of a first PMOS thin-film transistorand a first NMOS thin-film transistor electrically coupled to a true oneof the first pair of bit lines; and a stacked arrangement of a secondPMOS thin-film transistor and a second NMOS thin-film transistorelectrically coupled to a complementary one of the first pair of bitlines; and a pair of global bit lines electrically coupled to the firstand second NMOS thin-film transistors.
 8. The memory device of claim 7,further comprising: a pair of data lines; a precharge and equalizationcircuit electrically coupled to said pair of global bit lines; and aglobal bit line selection circuit electrically coupled to said prechargeand equalization circuit and said pair of data lines.
 9. The memorydevice of claim 7, further comprising: a second bit line precharge andselection circuit comprising: a stacked arrangement of a third PMOSthin-film transistor and a third NMOS thin-film transistor electricallycoupled to a true one of the second pair of bits lines; and a stackedarrangement of a fourth PMOS thin-film transistor and a fourth NMOSthin-film transistor electrically coupled to a complementary one of thesecond pair of bit lines.
 10. The memory device of claim 9, wherein saidpair of global bit lines is electrically coupled to the third and fourthNMOS thin-film transistors.
 11. The memory device of claim 10, furthercomprising: a pair of data lines; a precharge and equalization circuitelectrically coupled to said pair of global bit lines; and a global bitline selection circuit electrically coupled to said precharge andequalization circuit and said pair of data lines.
 12. An integratedcircuit memory device, comprising: a first column of TFT SRAM cellselectrically coupled to a first pair of bit lines; and a bit lineprecharge and selection circuit comprising a stacked arrangement of afirst PMOS TET and a first NMOS TFT electrically coupled to one of thefirst pair of bit lines.
 13. The memory device of claim 12, wherein afirst current carrying terminal of the PMOS TFT is electricallyconnected to a first current carrying terminal of the NMOS TFT and atrue one of the first pair of bit lines.
 14. The memory device of claim13, wherein a gate terminal of the PMOS TFT is electrically connected toa gate terminal of the NMOS TFT.
 15. The memory device of claim 14,wherein a second current carrying terminal of the PMOS TFT iselectrically connected to a power supply line and a second currentcarrying terminal of the NMOS TFT is electrically connected to a globalbit line.
 16. A static random access memory (SRAM) device, comprising:first and second columns of thin-film transistor (TFT) SRAM cellselectrically coupled to first and second pairs of bit lines,respectively; a first bit line precharge and selection circuitcomprising: a stacked arrangement of a first PMOS TFT and a first NMOSTET electrically coupled to a true one of the first pair of bit lines;and a stacked arrangement of a second PMOS TFT and a second NMOS TFTelectrically coupled to a complementary one of the first pair of bitlines; and a pair of global bit lines electrically coupled to the firstand second NMOS TFTs.
 17. The SRAM device of claim 16, furthercomprising: a pair of data lines; a precharge and equalization circuitelectrically coupled to said pair of global bit lines; and a global bitline selection circuit electrically coupled to said precharge andequalization circuit and said pair of data lines.
 18. The SRAM device ofclaim 16, further comprising: a second bit line precharge and selectioncircuit comprising: a stacked arrangement of a third PMOS TET and athird NMOS TFT electrically coupled to a true one of the second pair ofbits lines; and a stacked arrangement of a fourth PMOS TFT and a fourthNMOS TFT electrically coupled to a complementary one of the second pairof bit lines.
 19. The SRAM device of claim 18, wherein said pair ofglobal bit lines is electrically coupled to the third and fourth NMOSTFTs.
 20. The SRAM device of claim 19, further comprising: a pair ofdata lines; a precharge and equalization circuit electrically coupled tosaid pair of global bit lines; and a global bit line selection circuitelectrically coupled to said precharge and equalization circuit and saidpair of data lines.
 21. The SRAM device of claim 16, wherein each of theTFT SRAM cells is a 6T cell comprising four TFT transistors stacked overtwo planar transistors, which are disposed within a semiconductorsubstrate.
 22. The SRAM device of claim 21, wherein the four TFTtransistors includes two TFT PMOS pull-up transistors and two TFT NMOSaccess transistors; and wherein the two planar transistors include twoNMOS pull-down transistors.